Update DDB5476: make USB work and enable P2P bridge chip.

diff -Nru linux-2.4.16/arch/mips/ddb5xxx/ddb5476/setup.c.orig linux-2.4.16/arch/mips/ddb5xxx/ddb5476/setup.c
--- linux-2.4.16/arch/mips/ddb5xxx/ddb5476/setup.c.orig	Wed Nov 28 11:13:20 2001
+++ linux-2.4.16/arch/mips/ddb5xxx/ddb5476/setup.c	Thu Dec  6 18:30:03 2001
@@ -269,9 +269,9 @@
 	/* setup USB interrupt to IRQ 9, (bit 0:3 - 0001)
 	 * no IOCHRDY signal, (bit 7 - 1)
 	 * M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1)
-	 * Bypass USB Master INTAJ level to edge conversion (bit 4 - 0)
+	 * Make USB Master INTAJ level to edge conversion (bit 4 - 1)
 	 */
-	*(unsigned char *) 0xa8040074 = 0xc1;
+	*(unsigned char *) 0xa8040074 = 0xd1;
 
 	/* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011)
 	 * SCI routing to IRQ 13 disabled (bit 7 - 1)
diff -Nru linux-2.4.16/arch/mips/ddb5xxx/ddb5476/pci.c.orig linux-2.4.16/arch/mips/ddb5xxx/ddb5476/pci.c
--- linux-2.4.16/arch/mips/ddb5xxx/ddb5476/pci.c.orig	Wed Oct 17 12:46:04 2001
+++ linux-2.4.16/arch/mips/ddb5xxx/ddb5476/pci.c	Thu Dec  6 14:59:06 2001
@@ -52,10 +52,10 @@
 static unsigned char irq_map[MAX_SLOT_NUM] = {
 	/* SLOT:  0, AD:11 */ 0xff,
 	/* SLOT:  1, AD:12 */ 0xff,
-	/* SLOT:  2, AD:13 */ 9,
-	/* SLOT:  3, AD:14 */ 10,
+	/* SLOT:  2, AD:13 */ 9,		/* USB */
+	/* SLOT:  3, AD:14 */ 10,		/* PMU */
 	/* SLOT:  4, AD:15 */ 0xff,
-	/* SLOT:  5, AD:16 */ 0xff,
+	/* SLOT:  5, AD:16 */ 0x0,		/* P2P bridge */
 	/* SLOT:  6, AD:17 */ nile4_to_irq(PCI_EXT_INTB),
 	/* SLOT:  7, AD:18 */ nile4_to_irq(PCI_EXT_INTC),
 	/* SLOT:  8, AD:19 */ nile4_to_irq(PCI_EXT_INTD),
@@ -81,6 +81,14 @@
 
 	pci_for_each_dev(dev) {
 		slot_num = PCI_SLOT(dev->devfn);
+
+		/* we don't do IRQ fixup for sub-bus yet */
+		if (dev->bus->parent != NULL) {
+			db_run(printk("Don't know how to fixup irq for PCI device %d on sub-bus %d\n",
+				slot_num, dev->bus->number));
+			continue;
+		}
+
 		db_assert(slot_num < MAX_SLOT_NUM);
 		db_assert(irq_map[slot_num] != 0xff);
 
diff -Nru linux-2.4.16/arch/mips/ddb5xxx/ddb5476/pci_ops.c.orig linux-2.4.16/arch/mips/ddb5xxx/ddb5476/pci_ops.c
--- linux-2.4.16/arch/mips/ddb5xxx/ddb5476/pci_ops.c.orig	Wed Oct 17 12:46:04 2001
+++ linux-2.4.16/arch/mips/ddb5xxx/ddb5476/pci_ops.c	Thu Dec  6 14:46:24 2001
@@ -64,13 +64,25 @@
 	u32 option;
 
 	if (pci_config_workaround) {
-	/* [jsun] work around Vrc5476 controller itself */
-	if (slot_num == 12) slot_num = 0;
+		/* [jsun] work around Vrc5476 controller itself, returnning
+		 * slot 0 essentially makes vrc5476 invisible
+		 */ 
+		if (slot_num == 12) slot_num = 0;
+
+#if 0
+		/* BUG : skip P2P bridge for now */
+		if (slot_num == 5) slot_num = 0;
+#endif
 
-	/* BUG : skip P2P bridge for now */
-	if (slot_num == 5) slot_num = 0;
 	} else {
-		if (slot_num == 12) return DDB_BASE + DDB_PCI_BASE;
+		/* now we have to be hornest, returning the true
+		 * PCI config headers for vrc5476
+		 */ 
+		if (slot_num == 12) {
+			swap->pdar_backup = ddb_in32(swap->pdar);
+			swap->pmr_backup = ddb_in32(swap->pmr);
+			return DDB_BASE + DDB_PCI_BASE;
+		}
 	}
 
 	/* minimum pdar (window) size is 2MB */
@@ -101,7 +113,7 @@
 	} else {
 		/* type 1 config */
 		pci_addr = (bus << 16) | (slot_num << 11);
-		panic("ddb_access_config_base: we don't support type 1 config Yet");
+		/* panic("ddb_access_config_base: we don't support type 1 config Yet"); */
 	}
 
 	/*