diff -Nru link/arch/mips/kernel/entry.S.orig link/arch/mips/kernel/entry.S
--- link/arch/mips/kernel/entry.S.orig	Mon Jul  8 13:55:50 2002
+++ link/arch/mips/kernel/entry.S	Fri Jul 12 14:49:18 2002
@@ -114,6 +114,9 @@
 		.set	push
 		.set    mips3
 		.set	noat
+#if defined(R5432_CP0_INTERRUPT_WAR)
+		mfc0	k0, CP0_INDEX
+#endif
 		mfc0	k1, CP0_CAUSE
 		li	k0, 31<<2
 		andi	k1, k1, 0x7c
diff -Nru link/include/asm-mips/war.h.orig link/include/asm-mips/war.h
--- link/include/asm-mips/war.h.orig	Mon May 27 23:18:14 2002
+++ link/include/asm-mips/war.h	Fri Jul 12 14:54:06 2002
@@ -8,6 +8,8 @@
 #ifndef _ASM_WAR_H
 #define _ASM_WAR_H
 
+#include <linux/config.h>
+
 /*
  * Pleassures of the R4600 V1.x.  Cite from the IDT R4600 V1.7 errata:
  *
@@ -50,4 +52,19 @@
  */
 #define R4600_V2_HIT_CACHEOP_WAR
 
+#if defined(CONFIG_CPU_R5432)
+
+/*
+ * When an interrupt happens on a CP0 register read instruction, CPU may 
+ * lock up or read corrupted values of CP0 registers after it enters 
+ * the exception handler.  
+ *
+ * This workaround makes sure that we read a "safe" CP0 register as the
+ * first thing in the exception handler, which breaks one of the 
+ * pre-conditions for this problem.
+ */
+#define	R5432_CP0_INTERRUPT_WAR
+
+#endif
+
 #endif /* _ASM_WAR_H */