diff -Nru ./arch/mips/mm/c-r4k.c.orig ./arch/mips/mm/c-r4k.c
--- ./arch/mips/mm/c-r4k.c.orig	Wed Apr  9 17:16:14 2003
+++ ./arch/mips/mm/c-r4k.c	Wed Apr  9 18:22:56 2003
@@ -107,18 +107,12 @@
 	blast_dcache16_page_indexed(addr);
 	return;
 
-dc_32_lsb:
-	blast_dcache32_page_indexed(addr);
-	addr ^= 1UL;				/* Fall through */
-
 dc_32:
 	blast_dcache32_page_indexed(addr);
 	return;
 
 init:
-	if (current_cpu_data.cputype == CPU_R5432)
-		l = &&dc_32_lsb;
-	else if (dc_lsize == 16)
+	if (dc_lsize == 16)
 		l = &&dc_16;
 	else if (dc_lsize == 32)
 		l = &&dc_32;
@@ -135,17 +129,12 @@
 	blast_dcache16();
 	return;
 
-dc_32_lsb:
-	blast_dcache32_wayLSB();
-
 dc_32:
 	blast_dcache32();
 	return;
 
 init:
-	if (current_cpu_data.cputype == CPU_R5432)
-		l = &&dc_32_lsb;
-	else if (dc_lsize == 16)
+	if (dc_lsize == 16)
 		l = &&dc_16;
 	else if (dc_lsize == 32)
 		l = &&dc_32;
@@ -184,18 +173,12 @@
 	blast_icache16_page_indexed(addr);
 	return;
 
-ic_32_lsb:
-	blast_icache32_page_indexed(addr);
-	addr ^= 1UL;				/* Fall through */
-
 ic_32:
 	blast_icache32_page_indexed(addr);
 	return;
 
 init:
-	if (current_cpu_data.cputype == CPU_R5432)
-		l = &&ic_32_lsb;
-	else if (ic_lsize == 16)
+	if (ic_lsize == 16)
 		l = &&ic_16;
 	else if (ic_lsize == 32)
 		l = &&ic_32;
@@ -212,17 +195,12 @@
 	blast_icache16();
 	return;
 
-ic_32_lsb:
-	blast_icache32_wayLSB();
-
 ic_32:
 	blast_icache32();
 	return;
 
 init:
-	if (current_cpu_data.cputype == CPU_R5432)
-		l = &&ic_32_lsb;
-	else if (ic_lsize == 16)
+	if (ic_lsize == 16)
 		l = &&ic_16;
 	else if (ic_lsize == 32)
 		l = &&ic_32;
@@ -647,12 +625,21 @@
 	case CPU_R4700:
 	case CPU_R5000:
 	case CPU_NEVADA:
+		current_cpu_data.icache.ways = 2;
+		current_cpu_data.icache.wayoffset=
+			current_cpu_data.icache.linesz *
+			current_cpu_data.icache.sets;
+		break;
+
 	case CPU_R5432:
+	case CPU_R5500:
 		current_cpu_data.icache.ways = 2;
+		current_cpu_data.icache.wayoffset= 1;
 		break;
 
 	default:
 		current_cpu_data.icache.ways = 1;
+		current_cpu_data.icache.wayoffset = 1; 	/* doesn't matter */
 		break;
 	}
 
@@ -684,12 +671,21 @@
 	case CPU_R4700:
 	case CPU_R5000:
 	case CPU_NEVADA:
+		current_cpu_data.dcache.ways = 2;
+		current_cpu_data.icache.wayoffset=
+			current_cpu_data.icache.linesz *
+			current_cpu_data.icache.sets;
+		break;
+
 	case CPU_R5432:
+	case CPU_R5500:
 		current_cpu_data.dcache.ways = 2;
+		current_cpu_data.icache.wayoffset = 1;
 		break;
 
 	default:
 		current_cpu_data.dcache.ways = 1;
+		current_cpu_data.icache.wayoffset = 1;	/* does not matter */
 		break;
 	}
 
diff -Nru ./include/asm-mips/processor.h.orig ./include/asm-mips/processor.h
--- ./include/asm-mips/processor.h.orig	Wed Apr  9 14:39:46 2003
+++ ./include/asm-mips/processor.h	Wed Apr  9 17:48:01 2003
@@ -32,9 +32,10 @@
  * Descriptor for a cache
  */
 struct cache_desc {
-	int linesz;
+	short linesz;
+	short ways;
 	int sets;
-	int ways;
+	int wayoffset;	/* 1 << <way selection bit> */
 	int flags;	/* Details like write thru/back, coherent, etc. */
 };
 
diff -Nru ./include/asm-mips/r4kcache.h.orig ./include/asm-mips/r4kcache.h
--- ./include/asm-mips/r4kcache.h.orig	Wed Apr  9 14:39:46 2003
+++ ./include/asm-mips/r4kcache.h	Wed Apr  9 18:12:44 2003
@@ -126,26 +126,17 @@
 static inline void blast_dcache16(void)
 {
 	unsigned long start = KSEG0;
-	unsigned long end = start + dcache_size;
-
-	while (start < end) {
-		cache16_unroll32(start,Index_Writeback_Inv_D);
-		start += 0x200;
-	}
-}
-
-static inline void blast_dcache16_wayLSB(void)
-{
-	unsigned long start = KSEG0;
 	unsigned long end = start + current_cpu_data.dcache.sets *
 	                            current_cpu_data.dcache.linesz;
-	int way, ways = current_cpu_data.dcache.ways;
-
-	while (start < end) {
-		/* LSB of VA select the way */
-		for (way = 0; way < ways; way++)
-			cache16_unroll32(start|way,Index_Writeback_Inv_D);
-		start += 0x200;
+	int wayoffset = current_cpu_data.dcache.wayoffset;
+	int offsetend = current_cpu_data.dcache.ways * wayoffset;
+	int offset;
+
+	for (offset=0; offset < offsetend; offset+=wayoffset) {
+		while (start < end) {
+			cache16_unroll32(start|offset,Index_Writeback_Inv_D);
+			start += 0x200;
+		}
 	}
 }
 
@@ -164,24 +155,15 @@
 {
 	unsigned long start = page;
 	unsigned long end = start + PAGE_SIZE;
-
-	while (start < end) {
-		cache16_unroll32(start,Index_Writeback_Inv_D);
-		start += 0x200;
-	}
-}
-
-static inline void blast_dcache16_page_indexed_wayLSB(unsigned long page)
-{
-	unsigned long start = page;
-	unsigned long end = start + PAGE_SIZE;
-	int way, ways = current_cpu_data.dcache.ways;
-
-	while (start < end) {
-		/* LSB of VA select the way */
-		for (way = 0; way < ways; way++)
-			cache16_unroll32(start|way,Index_Writeback_Inv_D);
-		start += 0x200;
+	int wayoffset = current_cpu_data.dcache.wayoffset;
+	int offsetend = current_cpu_data.dcache.ways * wayoffset;
+	int offset;
+
+	for (offset=0; offset < offsetend; offset+=wayoffset) {
+		while (start < end) {
+			cache16_unroll32(start|offset,Index_Writeback_Inv_D);
+			start += 0x200;
+		}
 	}
 }
 
@@ -189,25 +171,15 @@
 {
 	unsigned long start = KSEG0;
 	unsigned long end = start + icache_size;
-
-	while (start < end) {
-		cache16_unroll32(start,Index_Invalidate_I);
-		start += 0x200;
-	}
-}
-
-static inline void blast_icache16_wayLSB(void)
-{
-	unsigned long start = KSEG0;
-	unsigned long end = start + current_cpu_data.icache.sets *
-	                            current_cpu_data.icache.linesz;
-	int way, ways = current_cpu_data.icache.ways;
-
-	while (start < end) {
-		/* LSB of VA select the way */
-		for (way = 0; way < ways; way++)
-			cache16_unroll32(start|way,Index_Invalidate_I);
-		start += 0x200;
+	int wayoffset = current_cpu_data.icache.wayoffset;
+	int offsetend = current_cpu_data.icache.ways * wayoffset;
+	int offset;
+
+	for (offset=0; offset < offsetend; offset+=wayoffset) {
+		while (start < end) {
+			cache16_unroll32(start|offset,Index_Invalidate_I);
+			start += 0x200;
+		}
 	}
 }
 
@@ -226,24 +198,15 @@
 {
 	unsigned long start = page;
 	unsigned long end = start + PAGE_SIZE;
-
-	while (start < end) {
-		cache16_unroll32(start,Index_Invalidate_I);
-		start += 0x200;
-	}
-}
-
-static inline void blast_icache16_page_indexed_wayLSB(unsigned long page)
-{
-	unsigned long start = page;
-	unsigned long end = start + PAGE_SIZE;
-	int way, ways = current_cpu_data.icache.ways;
-
-	while (start < end) {
-		/* LSB of VA select the way */
-		for (way = 0; way < ways; way++)
-			cache16_unroll32(start|way,Index_Invalidate_I);
-		start += 0x200;
+	int ways = current_cpu_data.icache.ways;
+	int wayoffset = current_cpu_data.icache.wayoffset;
+	int way, offset;
+
+	for (way=0, offset=0; way < ways; way++, offset+=wayoffset) {
+		while (start < end) {
+			cache16_unroll32(start|offset,Index_Invalidate_I);
+			start += 0x200;
+		}
 	}
 }
 
@@ -309,29 +272,21 @@
 static inline void blast_dcache32(void)
 {
 	unsigned long start = KSEG0;
-	unsigned long end = start + dcache_size;
-
-	while (start < end) {
-		cache32_unroll32(start,Index_Writeback_Inv_D);
-		start += 0x400;
-	}
-}
-
-static inline void blast_dcache32_wayLSB(void)
-{
-	unsigned long start = KSEG0;
 	unsigned long end = start + current_cpu_data.dcache.sets *
 	                            current_cpu_data.dcache.linesz;
-	int way, ways = current_cpu_data.dcache.ways;
-
-	while (start < end) {
-		/* LSB of VA select the way */
-		for (way = 0; way < ways; way++)
-			cache32_unroll32(start|way,Index_Writeback_Inv_D);
-		start += 0x400;
+	int ways = current_cpu_data.dcache.ways;
+	int wayoffset = current_cpu_data.dcache.wayoffset;
+	int way, offset;
+
+	for (way=0, offset=0; way < ways; way++, offset+=wayoffset) {
+		while (start < end) {
+			cache32_unroll32(start|offset,Index_Writeback_Inv_D);
+			start += 0x400;
+		}
 	}
 }
 
+
 /*
  * Call this function only with interrupts disabled or R4600 V2.0 may blow
  * up on you.
@@ -365,24 +320,15 @@
 {
 	unsigned long start = page;
 	unsigned long end = start + PAGE_SIZE;
-
-	while (start < end) {
-		cache32_unroll32(start,Index_Writeback_Inv_D);
-		start += 0x400;
-	}
-}
-
-static inline void blast_dcache32_page_indexed_wayLSB(unsigned long page)
-{
-	unsigned long start = page;
-	unsigned long end = start + PAGE_SIZE;
-	int way, ways = current_cpu_data.dcache.ways;
-
-	while (start < end) {
-		/* LSB of VA select the way */
-		for (way = 0; way < ways; way++)
-			cache32_unroll32(start|way,Index_Writeback_Inv_D);
-		start += 0x400;
+	int wayoffset = current_cpu_data.dcache.wayoffset;
+	int offsetend = current_cpu_data.dcache.ways * wayoffset;
+	int offset;
+
+	for (offset=0; offset < offsetend; offset+=wayoffset) {
+		while (start < end) {
+			cache32_unroll32(start|offset,Index_Writeback_Inv_D);
+			start += 0x400;
+		}
 	}
 }
 
@@ -390,25 +336,17 @@
 {
 	unsigned long start = KSEG0;
 	unsigned long end = start + icache_size;
-
-	while (start < end) {
-		cache32_unroll32(start,Index_Invalidate_I);
-		start += 0x400;
-	}
-}
-
-static inline void blast_icache32_wayLSB(void)
-{
-	unsigned long start = KSEG0;
 	unsigned long end = start + current_cpu_data.icache.sets *
 	                            current_cpu_data.icache.linesz;
-	int way, ways = current_cpu_data.icache.ways;
-
-	while (start < end) {
-		/* LSB of VA select the way */
-		for (way = 0; way < ways; way++)
-			cache32_unroll32(start|way,Index_Invalidate_I);
-		start += 0x400;
+	int wayoffset = current_cpu_data.icache.wayoffset;
+	int offsetend = current_cpu_data.icache.ways * wayoffset;
+	int offset;
+
+	for (offset=0; offset < offsetend; offset+=wayoffset) {
+		while (start < end) {
+			cache32_unroll32(start|offset,Index_Invalidate_I);
+			start += 0x400;
+		}
 	}
 }
 
@@ -427,24 +365,15 @@
 {
 	unsigned long start = page;
 	unsigned long end = start + PAGE_SIZE;
-
-	while (start < end) {
-		cache32_unroll32(start,Index_Invalidate_I);
-		start += 0x400;
-	}
-}
-
-static inline void blast_icache32_page_indexed_wayLSB(unsigned long page)
-{
-	unsigned long start = page;
-	unsigned long end = start + PAGE_SIZE;
-	int way, ways = current_cpu_data.icache.ways;
-
-	while (start < end) {
-		/* LSB of VA select the way */
-		for (way = 0; way < ways; way++)
-			cache32_unroll32(start|way,Index_Invalidate_I);
-		start += 0x400;
+	int wayoffset = current_cpu_data.icache.wayoffset;
+	int offsetend = current_cpu_data.icache.ways * wayoffset;
+	int offset;
+
+	for (offset=0; offset < offsetend; offset+=wayoffset) {
+		while (start < end) {
+			cache32_unroll32(start|offset,Index_Invalidate_I);
+			start += 0x400;
+		}
 	}
 }