Only applicable to some old malta boards.  Not worth to be
maintained in CVS tree.

The symptom is that CPU may execute from stale i-cache line
from trampoline even though flush_trampoline is correctly called
and executed.

Jun

diff -Nru link/arch/mips/mm/c-mips32.c.orig link/arch/mips/mm/c-mips32.c
--- link/arch/mips/mm/c-mips32.c.orig	Fri Nov 15 10:12:49 2002
+++ link/arch/mips/mm/c-mips32.c	Thu Dec  5 16:38:23 2002
@@ -409,8 +409,16 @@
  */
 static void mips32_flush_cache_sigtramp(unsigned long addr)
 {
+#if defined(CONFIG_4KC_STALE_CACHE_WORKAROUND)
+	unsigned long flags;
+	__save_and_cli(flags);
+	protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
+	blast_icache();
+	__restore_flags(flags);
+#else
 	protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
 	protected_flush_icache_line(addr & ~(ic_lsize - 1));
+#endif
 }
 
 /* Detect and size the various caches. */
diff -Nru link/arch/mips/config.in.orig link/arch/mips/config.in
--- link/arch/mips/config.in.orig	Wed Nov 13 10:18:42 2002
+++ link/arch/mips/config.in	Thu Dec  5 16:39:57 2002
@@ -198,6 +198,7 @@
    define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_SWAP_IO_SPACE y
    define_bool CONFIG_PC_KEYB y
+   define_bool CONFIG_4KC_STALE_CACHE_WORKAROUND y
 fi
 
 if [ "$CONFIG_MIPS_LXPB20K" = "y" ]; then