Index: arch/mips/ddb5xxx/ddb5477/pci.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/ddb5xxx/ddb5477/pci.c,v
retrieving revision 1.4.2.4
diff -u -r1.4.2.4 pci.c
--- arch/mips/ddb5xxx/ddb5477/pci.c	5 Aug 2002 23:53:31 -0000	1.4.2.4
+++ arch/mips/ddb5xxx/ddb5477/pci.c	12 Dec 2002 21:45:36 -0000
@@ -204,6 +204,33 @@
 {
 }
 
+/* 
+ * fixup baseboard AMD chip so that tx does not underflow.
+ *	bcr_18 |= 0x0800
+ * This sets NOUFLO bit which makes tx not start until whole pkt 
+ * is fetched to the chip.
+ */
+#define	PCNET32_WIO_RDP         0x10
+#define	PCNET32_WIO_RAP		0x12
+#define	PCNET32_WIO_RESET       0x14
+#define	PCNET32_WIO_BDP         0x16
+void __init fix_amd_lance(struct pci_dev *dev)
+{
+	unsigned long ioaddr;
+	u16 temp;
+
+	ioaddr=pci_resource_start(dev, 0);
+
+	inw(ioaddr + PCNET32_WIO_RESET);		/* reset chip */
+
+ 	/* bcr_18 |= 0x0800 */
+	outw (18, ioaddr + PCNET32_WIO_RAP);
+	temp = inw (ioaddr + PCNET32_WIO_BDP);
+	temp |= 0x0800;
+	outw (18, ioaddr + PCNET32_WIO_RAP);
+	outw (temp, ioaddr + PCNET32_WIO_BDP);
+}
+
 void __init pcibios_fixup(void)
 {
 	if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
@@ -241,6 +268,10 @@
 				pci_read_config_byte(dev, 0x41, &old);
 				pci_write_config_byte(dev, 0x41, old | 0xd0);
 			}
+
+			if (dev->vendor == PCI_VENDOR_ID_AMD && 
+					dev->device == PCI_DEVICE_ID_AMD_LANCE) 
+				fix_amd_lance(dev);
 		}
 
 	}