This one makes RTC work and works with standard i8259.c file. Sent to Ralf on 011005. Jun diff -Nru linux/arch/mips/ddb5xxx/ddb5476/dbg_io.c.rtcpatch linux/arch/mips/ddb5xxx/ddb5476/dbg_io.c --- linux/arch/mips/ddb5xxx/ddb5476/dbg_io.c.rtcpatch Fri Oct 5 16:34:01 2001 +++ linux/arch/mips/ddb5xxx/ddb5476/dbg_io.c Fri Oct 5 16:34:54 2001 @@ -0,0 +1,136 @@ +/* + * kgdb io functions for DDB5476. We use the second serial port. + * + * Copyright (C) 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +/* ======================= CONFIG ======================== */ + +/* [jsun] we use the second serial port for kdb */ +#define BASE 0xa60002f8 +#define MAX_BAUD 115200 + +/* distance in bytes between two serial registers */ +#define REG_OFFSET 1 + +/* + * 0 - kgdb does serial init + * 1 - kgdb skip serial init + */ +static int remoteDebugInitialized = 0; + +/* + * the default baud rate *if* kgdb does serial init + */ +#define BAUD_DEFAULT UART16550_BAUD_38400 + +/* ======================= END OF CONFIG ======================== */ + +typedef unsigned char uint8; +typedef unsigned int uint32; + +#define UART16550_BAUD_2400 2400 +#define UART16550_BAUD_4800 4800 +#define UART16550_BAUD_9600 9600 +#define UART16550_BAUD_19200 19200 +#define UART16550_BAUD_38400 38400 +#define UART16550_BAUD_57600 57600 +#define UART16550_BAUD_115200 115200 + +#define UART16550_PARITY_NONE 0 +#define UART16550_PARITY_ODD 0x08 +#define UART16550_PARITY_EVEN 0x18 +#define UART16550_PARITY_MARK 0x28 +#define UART16550_PARITY_SPACE 0x38 + +#define UART16550_DATA_5BIT 0x0 +#define UART16550_DATA_6BIT 0x1 +#define UART16550_DATA_7BIT 0x2 +#define UART16550_DATA_8BIT 0x3 + +#define UART16550_STOP_1BIT 0x0 +#define UART16550_STOP_2BIT 0x4 + +/* register offset */ +#define OFS_RCV_BUFFER 0 +#define OFS_TRANS_HOLD 0 +#define OFS_SEND_BUFFER 0 +#define OFS_INTR_ENABLE (1*REG_OFFSET) +#define OFS_INTR_ID (2*REG_OFFSET) +#define OFS_DATA_FORMAT (3*REG_OFFSET) +#define OFS_LINE_CONTROL (3*REG_OFFSET) +#define OFS_MODEM_CONTROL (4*REG_OFFSET) +#define OFS_RS232_OUTPUT (4*REG_OFFSET) +#define OFS_LINE_STATUS (5*REG_OFFSET) +#define OFS_MODEM_STATUS (6*REG_OFFSET) +#define OFS_RS232_INPUT (6*REG_OFFSET) +#define OFS_SCRATCH_PAD (7*REG_OFFSET) + +#define OFS_DIVISOR_LSB (0*REG_OFFSET) +#define OFS_DIVISOR_MSB (1*REG_OFFSET) + + +/* memory-mapped read/write of the port */ +#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) +#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) + +void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) +{ + /* disable interrupts */ + UART16550_WRITE(OFS_INTR_ENABLE, 0); + + /* set up buad rate */ + { + uint32 divisor; + + /* set DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x80); + + /* set divisor */ + divisor = MAX_BAUD / baud; + UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); + UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); + + /* clear DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x0); + } + + /* set data format */ + UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); +} + + +uint8 getDebugChar(void) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(BAUD_DEFAULT, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT); + } + + while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); + return UART16550_READ(OFS_RCV_BUFFER); +} + + +int putDebugChar(uint8 byte) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(BAUD_DEFAULT, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT); + } + + while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); + UART16550_WRITE(OFS_SEND_BUFFER, byte); + return 1; +} diff -Nru linux/arch/mips/ddb5xxx/ddb5476/pci.c.rtcpatch linux/arch/mips/ddb5xxx/ddb5476/pci.c --- linux/arch/mips/ddb5xxx/ddb5476/pci.c.rtcpatch Thu Oct 4 15:58:50 2001 +++ linux/arch/mips/ddb5xxx/ddb5476/pci.c Fri Oct 5 16:59:42 2001 @@ -16,7 +16,7 @@ static struct resource extpci_mem_resource = { "pci memory space", - DDB_PCI_MEM_BASE, + DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */ DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE -1, IORESOURCE_MEM}; diff -Nru linux/arch/mips/ddb5xxx/ddb5476/setup.c.rtcpatch linux/arch/mips/ddb5xxx/ddb5476/setup.c --- linux/arch/mips/ddb5xxx/ddb5476/setup.c.rtcpatch Thu Oct 4 16:03:20 2001 +++ linux/arch/mips/ddb5xxx/ddb5476/setup.c Fri Oct 5 17:19:45 2001 @@ -70,11 +70,21 @@ } extern void ddb_irq_setup(void); +extern void rtc_ds1386_init(unsigned long base); static void __init ddb_time_init(void) { printk("ddb_time_init invoked.\n"); mips_counter_frequency = 83000000; + + /* we have ds1396 RTC chip */ + rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE)); + + /* optional: we don't have a good way to set RTC time, + * so we will hack here to set a time. In normal running. + * it should *not* be called becaues RTC will keep the correct time. + */ + /* rtc_set_time(mktime(2001, 10, 05, 17, 20, 0)); */ } diff -Nru linux/arch/mips/ddb5xxx/ddb5476/nile4_pic.c.rtcpatch linux/arch/mips/ddb5xxx/ddb5476/nile4_pic.c --- linux/arch/mips/ddb5xxx/ddb5476/nile4_pic.c.rtcpatch Thu Oct 4 15:58:50 2001 +++ linux/arch/mips/ddb5xxx/ddb5476/nile4_pic.c Fri Oct 5 17:06:04 2001 @@ -157,7 +157,9 @@ /* restore window 0 for PCI I/O space */ // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32); ddb_out32(DDB_PCIINIT0, reg); - return irq; + + /* i8269.c set the base vector to be 0x20, as it does for i386 */ + return irq - 0x20; } #if defined(CONFIG_LL_DEBUG)