This patch does a bunch of assertion cleanups: . move debug.h from ddb5xxx to include/asm. . use lower case and db_ prefix . let vrc5477 ac97 dirver use its own debug macros . cosmetic changes. Jun 10/09/2001 diff -Nru linux/arch/mips/ddb5xxx/common/nile4.c.orig linux/arch/mips/ddb5xxx/common/nile4.c --- linux/arch/mips/ddb5xxx/common/nile4.c.orig Sun Jun 10 09:57:40 2001 +++ linux/arch/mips/ddb5xxx/common/nile4.c Mon Oct 8 17:43:58 2001 @@ -21,7 +21,6 @@ #include #include -#include u32 ddb_calc_pdar(u32 phys, u32 size, int width, diff -Nru linux/arch/mips/ddb5xxx/common/rtc_ds1386.c.orig linux/arch/mips/ddb5xxx/common/rtc_ds1386.c --- linux/arch/mips/ddb5xxx/common/rtc_ds1386.c.orig Fri Aug 24 10:49:16 2001 +++ linux/arch/mips/ddb5xxx/common/rtc_ds1386.c Tue Oct 9 09:59:36 2001 @@ -24,7 +24,7 @@ #include #include -#include +#include #define EPOCH 2000 @@ -147,7 +147,7 @@ /* remember the base */ rtc_base = base; - MIPS_ASSERT((rtc_base & 0xe0000000) == KSEG1); + db_assert((rtc_base & 0xe0000000) == KSEG1); /* turn on RTC if it is not on */ byte = READ_RTC(0x9); diff -Nru linux/arch/mips/ddb5xxx/ddb5477/irq.c.orig linux/arch/mips/ddb5xxx/ddb5477/irq.c --- linux/arch/mips/ddb5xxx/ddb5477/irq.c.orig Fri Aug 24 10:49:16 2001 +++ linux/arch/mips/ddb5xxx/ddb5477/irq.c Tue Oct 9 10:04:36 2001 @@ -18,10 +18,10 @@ #include #include +#include + #include -/* [jsun] sooner or later we should move this debug stuff to MIPS common */ -#include /* * IRQ mapping @@ -76,7 +76,7 @@ void ddb5477_irq_setup(void) { - MIPS_DEBUG(printk("ddb5477_irq_setup invoked.\n")); + db_run(printk("ddb5477_irq_setup invoked.\n")); /* by default, we disable all interrupts and route all vrc5477 * interrupts to pin 0 (irq 2) */ @@ -141,13 +141,13 @@ u32 bitmask; u32 i; - MIPS_ASSERT(ddb_in32(DDB_INT2STAT) == 0); - MIPS_ASSERT(ddb_in32(DDB_INT3STAT) == 0); - MIPS_ASSERT(ddb_in32(DDB_INT4STAT) == 0); - MIPS_ASSERT(ddb_in32(DDB_NMISTAT) == 0); + db_assert(ddb_in32(DDB_INT2STAT) == 0); + db_assert(ddb_in32(DDB_INT3STAT) == 0); + db_assert(ddb_in32(DDB_INT4STAT) == 0); + db_assert(ddb_in32(DDB_NMISTAT) == 0); if (ddb_in32(DDB_INT1STAT) != 0) { -#if defined(CONFIG_LL_DEBUG) +#if defined(CONFIG_DEBUG) vrc5477_show_int_regs(); #endif panic("error interrupt has happened.\n"); diff -Nru linux/arch/mips/ddb5xxx/ddb5477/irq_5477.c.orig linux/arch/mips/ddb5xxx/ddb5477/irq_5477.c --- linux/arch/mips/ddb5xxx/ddb5477/irq_5477.c.orig Sun Jun 10 09:57:41 2001 +++ linux/arch/mips/ddb5xxx/ddb5477/irq_5477.c Tue Oct 9 10:05:32 2001 @@ -23,10 +23,9 @@ #include #include -#include +#include -/* [jsun] sooner or later we should move this debug stuff to MIPS common */ -#include +#include /* number of total irqs supported by Vrc5477 */ #define NUM_5477_IRQ 32 @@ -37,9 +36,9 @@ static void vrc5477_irq_enable(unsigned int irq) { - MIPS_ASSERT(vrc5477_irq_base != -1); - MIPS_ASSERT(irq >= vrc5477_irq_base); - MIPS_ASSERT(irq < vrc5477_irq_base+ NUM_5477_IRQ); + db_assert(vrc5477_irq_base != -1); + db_assert(irq >= vrc5477_irq_base); + db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ); ll_vrc5477_irq_enable(irq - vrc5477_irq_base); } @@ -47,9 +46,9 @@ static void vrc5477_irq_disable(unsigned int irq) { - MIPS_ASSERT(vrc5477_irq_base != -1); - MIPS_ASSERT(irq >= vrc5477_irq_base); - MIPS_ASSERT(irq < vrc5477_irq_base + NUM_5477_IRQ); + db_assert(vrc5477_irq_base != -1); + db_assert(irq >= vrc5477_irq_base); + db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ); ll_vrc5477_irq_disable(irq - vrc5477_irq_base); } @@ -65,9 +64,9 @@ static void vrc5477_irq_ack(unsigned int irq) { - MIPS_ASSERT(vrc5477_irq_base != -1); - MIPS_ASSERT(irq >= vrc5477_irq_base); - MIPS_ASSERT(irq < vrc5477_irq_base+ NUM_5477_IRQ); + db_assert(vrc5477_irq_base != -1); + db_assert(irq >= vrc5477_irq_base); + db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ); /* clear the interrupt bit */ /* some irqs require the driver to clear the sources */ @@ -82,9 +81,9 @@ static void vrc5477_irq_end(unsigned int irq) { - MIPS_ASSERT(vrc5477_irq_base != -1); - MIPS_ASSERT(irq >= vrc5477_irq_base); - MIPS_ASSERT(irq < vrc5477_irq_base + NUM_5477_IRQ); + db_assert(vrc5477_irq_base != -1); + db_assert(irq >= vrc5477_irq_base); + db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ); ll_vrc5477_irq_enable( irq - vrc5477_irq_base); } @@ -119,8 +118,8 @@ int vrc5477_irq_to_irq(int irq) { - MIPS_ASSERT(irq >= 0); - MIPS_ASSERT(irq < NUM_5477_IRQ); + db_assert(irq >= 0); + db_assert(irq < NUM_5477_IRQ); return irq + vrc5477_irq_base; } @@ -131,10 +130,10 @@ u32 reg_bitmask; u32 reg_index; - MIPS_ASSERT(vrc5477_irq >= 0); - MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ); - MIPS_ASSERT(ip >= 0); - MIPS_ASSERT((ip < 5) || (ip == 6)); + db_assert(vrc5477_irq >= 0); + db_assert(vrc5477_irq < NUM_5477_IRQ); + db_assert(ip >= 0); + db_assert((ip < 5) || (ip == 6)); reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4; reg_value = ddb_in32(reg_index); @@ -150,13 +149,13 @@ u32 reg_bitmask; u32 reg_index; - MIPS_ASSERT(vrc5477_irq >= 0); - MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ); + db_assert(vrc5477_irq >= 0); + db_assert(vrc5477_irq < NUM_5477_IRQ); reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4; reg_value = ddb_in32(reg_index); reg_bitmask = 8 << (vrc5477_irq % 8 * 4); - MIPS_ASSERT((reg_value & reg_bitmask) == 0); + db_assert((reg_value & reg_bitmask) == 0); ddb_out32(reg_index, reg_value | reg_bitmask); } @@ -166,14 +165,14 @@ u32 reg_bitmask; u32 reg_index; - MIPS_ASSERT(vrc5477_irq >= 0); - MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ); + db_assert(vrc5477_irq >= 0); + db_assert(vrc5477_irq < NUM_5477_IRQ); reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4; reg_value = ddb_in32(reg_index); reg_bitmask = 8 << (vrc5477_irq % 8 * 4); /* we assert that the interrupt is enabled (perhaps over-zealous) */ - MIPS_ASSERT( (reg_value & reg_bitmask) != 0); + db_assert( (reg_value & reg_bitmask) != 0); ddb_out32(reg_index, reg_value & ~reg_bitmask); } diff -Nru linux/arch/mips/ddb5xxx/ddb5477/pci.c.orig linux/arch/mips/ddb5xxx/ddb5477/pci.c --- linux/arch/mips/ddb5xxx/ddb5477/pci.c.orig Tue Oct 2 10:14:39 2001 +++ linux/arch/mips/ddb5xxx/ddb5477/pci.c Tue Oct 9 10:05:57 2001 @@ -1,12 +1,25 @@ +/* + * PCI code for DDB5477. + * + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + #include #include #include #include #include +#include #include -#include static struct resource extpci_io_resource = { "ext pci IO space", @@ -104,8 +117,8 @@ pci_for_each_dev(dev) { slot_num = PCI_SLOT(dev->devfn); - MIPS_ASSERT(slot_num < MAX_SLOT_NUM); - MIPS_ASSERT(irq_map[slot_num] != 0xff); + db_assert(slot_num < MAX_SLOT_NUM); + db_assert(irq_map[slot_num] != 0xff); pci_write_config_byte(dev, PCI_INTERRUPT_LINE, @@ -114,7 +127,7 @@ } } -#if defined(CONFIG_LL_DEBUG) +#if defined(CONFIG_DEBUG) extern void jsun_scan_pci_bus(void); extern void jsun_assign_pci_resource(void); #endif diff -Nru linux/arch/mips/ddb5xxx/ddb5477/pci_ops.c.orig linux/arch/mips/ddb5xxx/ddb5477/pci_ops.c --- linux/arch/mips/ddb5xxx/ddb5477/pci_ops.c.orig Sun Jun 10 09:57:41 2001 +++ linux/arch/mips/ddb5xxx/ddb5477/pci_ops.c Tue Oct 9 10:06:56 2001 @@ -26,7 +26,8 @@ #include #include -#include +#include + #include /* @@ -76,10 +77,10 @@ // if (slot_num == 4) slot_num = 0; /* minimum pdar (window) size is 2MB */ - MIPS_ASSERT(swap->config_size >= (2 << 20)); + db_assert(swap->config_size >= (2 << 20)); - MIPS_ASSERT(slot_num < (1 << 5)); - MIPS_ASSERT(bus < (1 << 8)); + db_assert(slot_num < (1 << 5)); + db_assert(bus < (1 << 8)); /* backup registers */ swap->pdar_backup = ddb_in32(swap->pdar); @@ -115,7 +116,7 @@ virt_addr = KSEG1ADDR(swap->config_base + pci_addr); pciinit_offset = 0; } else { - MIPS_ASSERT( (pci_addr & (swap->config_size - 1)) == 0); + db_assert( (pci_addr & (swap->config_size - 1)) == 0); virt_addr = KSEG1ADDR(swap->config_base); pciinit_offset = pci_addr; } @@ -142,13 +143,13 @@ u32 bus, slot_num, func_num; u32 base; - MIPS_ASSERT((where & 3) == 0); - MIPS_ASSERT(where < (1 << 8)); + db_assert((where & 3) == 0); + db_assert(where < (1 << 8)); /* check if the bus is top-level */ if (dev->bus->parent != NULL) { bus = dev->bus->number; - MIPS_ASSERT(bus != 0); + db_assert(bus != 0); } else { bus = 0; } @@ -169,7 +170,7 @@ int status; u32 result; - MIPS_ASSERT((where & 1) == 0); + db_assert((where & 1) == 0); status = read_config_dword(swap, dev, where & ~3, &result); if (where & 2) result >>= 16; @@ -200,13 +201,13 @@ u32 bus, slot_num, func_num; u32 base; - MIPS_ASSERT((where & 3) == 0); - MIPS_ASSERT(where < (1 << 8)); + db_assert((where & 3) == 0); + db_assert(where < (1 << 8)); /* check if the bus is top-level */ if (dev->bus->parent != NULL) { bus = dev->bus->number; - MIPS_ASSERT(bus != 0); + db_assert(bus != 0); } else { bus = 0; } @@ -227,7 +228,7 @@ int status, shift=0; u32 result; - MIPS_ASSERT((where & 1) == 0); + db_assert((where & 1) == 0); status = read_config_dword(swap, dev, where & ~3, &result); if (status != PCIBIOS_SUCCESSFUL) return status; @@ -303,7 +304,7 @@ iopci_write_config_dword }; -#if defined(CONFIG_LL_DEBUG) +#if defined(CONFIG_DEBUG) void jsun_scan_pci_bus(void) { struct pci_bus bus; @@ -332,26 +333,26 @@ int i; dev.devfn = devfn; - MIPS_VERIFY(pci_read_config_dword(&dev, 0, &temp), - == PCIBIOS_SUCCESSFUL); + db_verify(pci_read_config_dword(&dev, 0, &temp), + == PCIBIOS_SUCCESSFUL); if (temp == 0xffffffff) continue; printk("slot %d: (addr %d) \n", devfn/8, 11+devfn/8); /* verify read word and byte */ - MIPS_VERIFY(pci_read_config_word(&dev, 2, &temp16), - == PCIBIOS_SUCCESSFUL); - MIPS_ASSERT(temp16 == (temp >> 16)); - MIPS_VERIFY(pci_read_config_byte(&dev, 3, &temp8), - == PCIBIOS_SUCCESSFUL); - MIPS_ASSERT(temp8 == (temp >> 24)); - MIPS_VERIFY(pci_read_config_byte(&dev, 1, &temp8), - == PCIBIOS_SUCCESSFUL); - MIPS_ASSERT(temp8 == ((temp >> 8) & 0xff)); + db_verify(pci_read_config_word(&dev, 2, &temp16), + == PCIBIOS_SUCCESSFUL); + db_assert(temp16 == (temp >> 16)); + db_verify(pci_read_config_byte(&dev, 3, &temp8), + == PCIBIOS_SUCCESSFUL); + db_assert(temp8 == (temp >> 24)); + db_verify(pci_read_config_byte(&dev, 1, &temp8), + == PCIBIOS_SUCCESSFUL); + db_assert(temp8 == ((temp >> 8) & 0xff)); for (i=0; i < 16; i++) { - MIPS_VERIFY(pci_read_config_dword(&dev, i*4, &temp), - == PCIBIOS_SUCCESSFUL); + db_verify(pci_read_config_dword(&dev, i*4, &temp), + == PCIBIOS_SUCCESSFUL); printk("\t%08X", temp); if ((i%4) == 3) printk("\n"); } @@ -374,7 +375,7 @@ /* for slot 5 (ext pci 1) eepro card */ dev.devfn = 5*8; pci_read_config_dword(&dev, 0, &temp); - MIPS_ASSERT(temp == 0x12298086); + db_assert(temp == 0x12298086); pci_write_config_dword(&dev, PCI_BASE_ADDRESS_0, DDB_PCI0_MEM_BASE); pci_write_config_dword(&dev, PCI_BASE_ADDRESS_1, 0); @@ -396,7 +397,7 @@ /* for slot 4 on board ether chip */ dev.devfn = 4*8; pci_read_config_dword(&dev, 0, &temp); - MIPS_ASSERT(temp == 0x00191011); + db_assert(temp == 0x00191011); pci_write_config_dword(&dev, PCI_BASE_ADDRESS_0, 0x1000); pci_write_config_dword(&dev, PCI_BASE_ADDRESS_1, DDB_PCI0_MEM_BASE); diff -Nru linux/arch/mips/ddb5xxx/ddb5477/setup.c.orig linux/arch/mips/ddb5xxx/ddb5477/setup.c --- linux/arch/mips/ddb5xxx/ddb5477/setup.c.orig Sun Jun 10 09:57:41 2001 +++ linux/arch/mips/ddb5xxx/ddb5477/setup.c Tue Oct 9 10:07:41 2001 @@ -33,6 +33,7 @@ #include #include #include +#include #include @@ -60,7 +61,7 @@ /* CPU cold reset */ t = ddb_in32(DDB_CPUSTAT); - MIPS_ASSERT((t&1)); + db_assert((t&1)); ddb_out32(DDB_CPUSTAT, t); /* Call the PROM */ @@ -90,7 +91,7 @@ rtc_ds1386_init(KSEG1ADDR(DDB_LCS1_BASE)); } -#if defined(CONFIG_LL_DEBUG) +#if defined(CONFIG_DEBUG) int board_init_done_flag = 0; #endif @@ -117,7 +118,7 @@ #endif /* this is the last board dependent code */ - MIPS_DEBUG(board_init_done_flag = 1); + db_run(board_init_done_flag = 1); } static void ddb5477_board_init(void); @@ -164,11 +165,11 @@ /* ----------- setup PDARs ------------ */ /* SDRAM should have been set */ - MIPS_ASSERT(ddb_in32(DDB_SDRAM0) == + db_assert(ddb_in32(DDB_SDRAM0) == ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1)); /* SDRAM1 should be turned off. What is this for anyway ? */ - MIPS_ASSERT( (ddb_in32(DDB_SDRAM1) & 0xf) == 0); + db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0); /* Set LDCSs */ /* flash */ @@ -179,12 +180,12 @@ ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0); /* verify VRC5477 base addr */ - MIPS_ASSERT(ddb_in32(DDB_VRC5477) == - ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1)); + db_assert(ddb_in32(DDB_VRC5477) == + ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1)); /* verify BOOT ROM addr */ - MIPS_ASSERT(ddb_in32(DDB_BOOTCS) == - ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0)); + db_assert(ddb_in32(DDB_BOOTCS) == + ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0)); /* setup PCI windows - window0 for MEM/config, window1 for IO */ ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1); diff -Nru linux/arch/mips/ddb5xxx/ddb5477/debug.c.orig linux/arch/mips/ddb5xxx/ddb5477/debug.c diff -Nru linux/arch/mips/ddb5xxx/ddb5477/Makefile.orig linux/arch/mips/ddb5xxx/ddb5477/Makefile --- linux/arch/mips/ddb5xxx/ddb5477/Makefile.orig Sun Jun 10 09:57:41 2001 +++ linux/arch/mips/ddb5xxx/ddb5477/Makefile Mon Oct 8 18:33:42 2001 @@ -15,7 +15,7 @@ obj-y += int-handler.o irq.o irq_5477.o setup.o pci.o pci_ops.o -obj-$(CONFIG_LL_DEBUG) += debug.o +obj-$(CONFIG_DEBUG) += debug.o obj-$(CONFIG_REMOTE_DEBUG) += kgdb_io.o obj-$(CONFIG_BLK_DEV_INITRD) += ramdisk.o diff -Nru linux/arch/mips/ddb5xxx/ddb5476/pci.c.orig linux/arch/mips/ddb5xxx/ddb5476/pci.c --- linux/arch/mips/ddb5xxx/ddb5476/pci.c.orig Sat Oct 6 17:09:48 2001 +++ linux/arch/mips/ddb5xxx/ddb5476/pci.c Tue Oct 9 10:01:09 2001 @@ -4,9 +4,9 @@ #include #include +#include #include -#include static struct resource extpci_io_resource = { "pci IO space", @@ -81,8 +81,8 @@ pci_for_each_dev(dev) { slot_num = PCI_SLOT(dev->devfn); - MIPS_ASSERT(slot_num < MAX_SLOT_NUM); - MIPS_ASSERT(irq_map[slot_num] != 0xff); + db_assert(slot_num < MAX_SLOT_NUM); + db_assert(irq_map[slot_num] != 0xff); pci_write_config_byte(dev, PCI_INTERRUPT_LINE, @@ -91,7 +91,7 @@ } } -#if defined(CONFIG_LL_DEBUG) +#if defined(CONFIG_DEBUG) extern void jsun_scan_pci_bus(void); #endif diff -Nru linux/arch/mips/ddb5xxx/ddb5476/pci_ops.c.orig linux/arch/mips/ddb5xxx/ddb5476/pci_ops.c --- linux/arch/mips/ddb5xxx/ddb5476/pci_ops.c.orig Sat Oct 6 17:09:48 2001 +++ linux/arch/mips/ddb5xxx/ddb5476/pci_ops.c Tue Oct 9 10:02:24 2001 @@ -2,7 +2,7 @@ * Copyright 2001 MontaVista Software Inc. * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net * - * arch/mips/ddb5xxx/ddb5477/pci_ops.c + * arch/mips/ddb5xxx/ddb5476/pci_ops.c * Define the pci_ops for DB5477. * * Much of the code is derived from the original DDB5074 port by @@ -21,8 +21,8 @@ #include #include +#include -#include #include /* @@ -74,10 +74,10 @@ } /* minimum pdar (window) size is 2MB */ - MIPS_ASSERT(swap->config_size >= (2 << 20)); + db_assert(swap->config_size >= (2 << 20)); - MIPS_ASSERT(slot_num < (1 << 5)); - MIPS_ASSERT(bus < (1 << 8)); + db_assert(slot_num < (1 << 5)); + db_assert(bus < (1 << 8)); /* backup registers */ swap->pdar_backup = ddb_in32(swap->pdar); @@ -113,7 +113,7 @@ virt_addr = KSEG1ADDR(swap->config_base + pci_addr); pciinit_offset = 0; } else { - MIPS_ASSERT( (pci_addr & (swap->config_size - 1)) == 0); + db_assert( (pci_addr & (swap->config_size - 1)) == 0); virt_addr = KSEG1ADDR(swap->config_base); pciinit_offset = pci_addr; } @@ -140,13 +140,13 @@ u32 bus, slot_num, func_num; u32 base; - MIPS_ASSERT((where & 3) == 0); - MIPS_ASSERT(where < (1 << 8)); + db_assert((where & 3) == 0); + db_assert(where < (1 << 8)); /* check if the bus is top-level */ if (dev->bus->parent != NULL) { bus = dev->bus->number; - MIPS_ASSERT(bus != 0); + db_assert(bus != 0); } else { bus = 0; } @@ -167,7 +167,7 @@ int status; u32 result; - MIPS_ASSERT((where & 1) == 0); + db_assert((where & 1) == 0); status = read_config_dword(swap, dev, where & ~3, &result); if (where & 2) result >>= 16; @@ -198,13 +198,13 @@ u32 bus, slot_num, func_num; u32 base; - MIPS_ASSERT((where & 3) == 0); - MIPS_ASSERT(where < (1 << 8)); + db_assert((where & 3) == 0); + db_assert(where < (1 << 8)); /* check if the bus is top-level */ if (dev->bus->parent != NULL) { bus = dev->bus->number; - MIPS_ASSERT(bus != 0); + db_assert(bus != 0); } else { bus = 0; } @@ -225,7 +225,7 @@ int status, shift=0; u32 result; - MIPS_ASSERT((where & 1) == 0); + db_assert((where & 1) == 0); status = read_config_dword(swap, dev, where & ~3, &result); if (status != PCIBIOS_SUCCESSFUL) return status; @@ -284,7 +284,7 @@ }; -#if defined(CONFIG_LL_DEBUG) +#if defined(CONFIG_DEBUG) void jsun_scan_pci_bus(void) { struct pci_bus bus; @@ -310,7 +310,7 @@ int i; dev.devfn = devfn; - MIPS_VERIFY(pci_read_config_dword(&dev, 0, &temp), + db_verify(pci_read_config_dword(&dev, 0, &temp), == PCIBIOS_SUCCESSFUL); if (temp == 0xffffffff) continue; @@ -318,21 +318,21 @@ 11+devfn/8); /* verify read word and byte */ - MIPS_VERIFY(pci_read_config_word(&dev, 2, &temp16), - == PCIBIOS_SUCCESSFUL); - MIPS_ASSERT(temp16 == (temp >> 16)); - MIPS_VERIFY(pci_read_config_byte(&dev, 3, &temp8), - == PCIBIOS_SUCCESSFUL); - MIPS_ASSERT(temp8 == (temp >> 24)); - MIPS_VERIFY(pci_read_config_byte(&dev, 1, &temp8), - == PCIBIOS_SUCCESSFUL); - MIPS_ASSERT(temp8 == ((temp >> 8) & 0xff)); + db_verify(pci_read_config_word(&dev, 2, &temp16), + == PCIBIOS_SUCCESSFUL); + db_assert(temp16 == (temp >> 16)); + db_verify(pci_read_config_byte(&dev, 3, &temp8), + == PCIBIOS_SUCCESSFUL); + db_assert(temp8 == (temp >> 24)); + db_verify(pci_read_config_byte(&dev, 1, &temp8), + == PCIBIOS_SUCCESSFUL); + db_assert(temp8 == ((temp >> 8) & 0xff)); for (i=0; i < 16; i++) { if ((i%4) == 0) printk(KERN_INFO); - MIPS_VERIFY(pci_read_config_dword(&dev, i*4, &temp), - == PCIBIOS_SUCCESSFUL); + db_verify(pci_read_config_dword(&dev, i*4, &temp), + == PCIBIOS_SUCCESSFUL); printk("\t%08X", temp); if ((i%4) == 3) printk("\n"); diff -Nru linux/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c.orig linux/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c --- linux/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c.orig Sat Oct 6 17:09:48 2001 +++ linux/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c Mon Oct 8 17:50:37 2001 @@ -18,7 +18,6 @@ #include #include -#include static int irq_base; diff -Nru linux/arch/mips/ddb5xxx/ddb5476/irq.c.orig linux/arch/mips/ddb5xxx/ddb5476/irq.c --- linux/arch/mips/ddb5xxx/ddb5476/irq.c.orig Sat Oct 6 17:09:48 2001 +++ linux/arch/mips/ddb5xxx/ddb5476/irq.c Mon Oct 8 17:48:18 2001 @@ -3,6 +3,11 @@ * * Copyright (C) 2000 Geert Uytterhoeven * Sony Software Development Center Europe (SDCE), Brussels + * + * Re-write the whole thing to use new irq.c file. + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * */ #include #include diff -Nru linux/arch/mips/ddb5xxx/ddb5476/setup.c.orig linux/arch/mips/ddb5xxx/ddb5476/setup.c --- linux/arch/mips/ddb5xxx/ddb5476/setup.c.orig Sat Oct 6 17:09:48 2001 +++ linux/arch/mips/ddb5xxx/ddb5476/setup.c Tue Oct 9 10:03:15 2001 @@ -24,6 +24,7 @@ #include #include #include +#include #include @@ -189,11 +190,11 @@ { /* ----------- setup PDARs ------------ */ /* check SDRAM0, whether we are on MEM bus does not matter */ - MIPS_ASSERT((ddb_in32(DDB_SDRAM0) & 0xffffffef) == - ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1)); + db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) == + ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1)); /* SDRAM1 should be turned off. What is this for anyway ? */ - MIPS_ASSERT( (ddb_in32(DDB_SDRAM1) & 0xf) == 0); + db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0); /* flash 1&2, DDB status, DDB control */ ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0); @@ -208,13 +209,13 @@ /* verify VRC5477 base addr */ /* don't care about some details */ - MIPS_ASSERT((ddb_in32(DDB_INTCS) & 0xffffff0f) == - ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0)); + db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) == + ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0)); /* verify BOOT ROM addr */ /* don't care about some details */ - MIPS_ASSERT((ddb_in32(DDB_BOOTCS) & 0xffffff0f) == - ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0)); + db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) == + ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0)); /* setup PCI windows - window1 for MEM/config, window0 for IO */ ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1); diff -Nru linux/arch/mips/config.in.orig linux/arch/mips/config.in --- linux/arch/mips/config.in.orig Mon Oct 8 11:00:27 2001 +++ linux/arch/mips/config.in Mon Oct 8 17:33:59 2001 @@ -507,9 +507,7 @@ bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG dep_bool 'Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_REMOTE_DEBUG fi -if [ "$CONFIG_SERIAL" = "y" ]; then - bool 'Low-level debugging' CONFIG_LL_DEBUG -fi +bool 'Enable run-time debugging' CONFIG_DEBUG bool 'Magic SysRq key' CONFIG_MAGIC_SYSRQ if [ "$CONFIG_SMP" != "y" ]; then bool 'Run uncached' CONFIG_MIPS_UNCACHED diff -Nru linux/arch/mips/defconfig-ddb5477.orig linux/arch/mips/defconfig-ddb5477 --- linux/arch/mips/defconfig-ddb5477.orig Tue Oct 2 10:14:38 2001 +++ linux/arch/mips/defconfig-ddb5477 Mon Oct 8 18:14:29 2001 @@ -465,6 +465,6 @@ CONFIG_CROSSCOMPILE=y # CONFIG_REMOTE_DEBUG is not set # CONFIG_GDB_CONSOLE is not set -CONFIG_LL_DEBUG=y +CONFIG_DEBUG=y # CONFIG_MAGIC_SYSRQ is not set # CONFIG_MIPS_UNCACHED is not set diff -Nru linux/arch/mips/defconfig-ddb5476.orig linux/arch/mips/defconfig-ddb5476 --- linux/arch/mips/defconfig-ddb5476.orig Mon Oct 8 11:00:27 2001 +++ linux/arch/mips/defconfig-ddb5476 Mon Oct 8 18:44:38 2001 @@ -582,6 +582,6 @@ CONFIG_CROSSCOMPILE=y # CONFIG_REMOTE_DEBUG is not set # CONFIG_GDB_CONSOLE is not set -CONFIG_LL_DEBUG=y +CONFIG_DEBUG=y # CONFIG_MAGIC_SYSRQ is not set # CONFIG_MIPS_UNCACHED is not set diff -Nru linux/drivers/sound/nec_vrc5477.c.orig linux/drivers/sound/nec_vrc5477.c --- linux/drivers/sound/nec_vrc5477.c.orig Fri Aug 24 10:50:01 2001 +++ linux/drivers/sound/nec_vrc5477.c Mon Oct 8 18:11:45 2001 @@ -83,17 +83,25 @@ #include #include -#include +/* -------------------debug macros -------------------------------------- */ +/* #undef VRC5477_AC97_DEBUG */ +#define VRC5477_AC97_DEBUG #undef VRC5477_AC97_VERBOSE_DEBUG +/* #define VRC5477_AC97_VERBOSE_DEBUG */ -/* one must turn on CONFIG_LL_DEBUG before VERBOSE_DEBUG is turned */ #if defined(VRC5477_AC97_VERBOSE_DEBUG) -#if !defined(CONFIG_LL_DEBUG) -#error "You must turn CONFIG_LL_DEBUG" -#endif +#define VRC5477_AC97_DEBUG #endif +#if defined(VRC5477_AC97_DEBUG) +#include +#define ASSERT(x) if (!(x)) { \ + panic("assertion failed at %s:%d: %s\n", __FILE__, __LINE__, #x); } +#else +#define ASSERT(x) +#endif /* VRC5477_AC97_DEBUG */ + #if defined(VRC5477_AC97_VERBOSE_DEBUG) static u16 inTicket=0; /* check sync between intr & write */ static u16 outTicket=0; @@ -179,11 +187,11 @@ unsigned long io; unsigned int irq; -#ifdef CONFIG_LL_DEBUG +#ifdef VRC5477_AC97_DEBUG /* debug /proc entry */ struct proc_dir_entry *ps; struct proc_dir_entry *ac97_ps; -#endif /* CONFIG_LL_DEBUG */ +#endif /* VRC5477_AC97_DEBUG */ struct ac97_codec codec; @@ -275,7 +283,7 @@ (VRC5477_CODEC_RD_RRDYA | VRC5477_CODEC_RD_RRDYD) ) { /* we get either addr or data, or both */ if (result & VRC5477_CODEC_RD_RRDYA) { - MIPS_ASSERT(addr == ((result >> 16) & 0x7f) ); + ASSERT(addr == ((result >> 16) & 0x7f) ); } if (result & VRC5477_CODEC_RD_RRDYD) { break; @@ -408,7 +416,7 @@ } /* we should have some data to do the DMA trasnfer */ - MIPS_ASSERT(db->count >= db->fragSize); + ASSERT(db->count >= db->fragSize); /* clear pending fales interrupts */ outl(VRC5477_INT_MASK_DAC1END | VRC5477_INT_MASK_DAC2END, @@ -442,12 +450,12 @@ outl (temp, s->io + VRC5477_CTRL); /* it is time to setup next dma transfer */ - MIPS_ASSERT(inl(s->io + VRC5477_DAC1_CTRL) & VRC5477_DMA_WIP); - MIPS_ASSERT(inl(s->io + VRC5477_DAC2_CTRL) & VRC5477_DMA_WIP); + ASSERT(inl(s->io + VRC5477_DAC1_CTRL) & VRC5477_DMA_WIP); + ASSERT(inl(s->io + VRC5477_DAC2_CTRL) & VRC5477_DMA_WIP); temp = db->nextOut + db->fragSize; if (temp >= db->fragTotalSize) { - MIPS_ASSERT(temp == db->fragTotalSize); + ASSERT(temp == db->fragTotalSize); temp = 0; } @@ -463,7 +471,7 @@ #if defined(VRC5477_AC97_VERBOSE_DEBUG) outTicket = *(u16*)(db->lbuf+db->nextOut); if (db->count > db->fragSize) { - MIPS_ASSERT((u16)(outTicket+1) == *(u16*)(db->lbuf+temp)); + ASSERT((u16)(outTicket+1) == *(u16*)(db->lbuf+temp)); } #endif @@ -521,7 +529,7 @@ } /* we should at least have some free space in the buffer */ - MIPS_ASSERT(db->count < db->fragTotalSize - db->fragSize * 2); + ASSERT(db->count < db->fragTotalSize - db->fragSize * 2); /* clear pending ones */ outl(VRC5477_INT_MASK_ADC1END | VRC5477_INT_MASK_ADC2END, @@ -553,7 +561,7 @@ /* it is time to setup next dma transfer */ temp = db->nextIn + db->fragSize; if (temp >= db->fragTotalSize) { - MIPS_ASSERT(temp == db->fragTotalSize); + ASSERT(temp == db->fragTotalSize); temp = 0; } outl(db->lbufDma + temp, s->io + VRC5477_ADC1_BADDR); @@ -573,7 +581,7 @@ struct dmabuf *db) { if (db->lbuf) { - MIPS_ASSERT(db->rbuf); + ASSERT(db->rbuf); pci_free_consistent(s->dev, PAGE_SIZE << db->bufOrder, db->lbuf, db->lbufDma); pci_free_consistent(s->dev, PAGE_SIZE << db->bufOrder, @@ -592,7 +600,7 @@ unsigned bufsize; if (!db->lbuf) { - MIPS_ASSERT(!db->rbuf); + ASSERT(!db->rbuf); db->ready = 0; for (order = DMABUF_DEFAULTORDER; @@ -606,7 +614,7 @@ &db->rbufDma); if (db->lbuf && db->rbuf) break; if (db->lbuf) { - MIPS_ASSERT(!db->rbuf); + ASSERT(!db->rbuf); pci_free_consistent(s->dev, PAGE_SIZE << order, db->lbuf, @@ -614,7 +622,7 @@ } } if (!db->lbuf) { - MIPS_ASSERT(!db->rbuf); + ASSERT(!db->rbuf); return -ENOMEM; } @@ -677,7 +685,7 @@ /* set the base addr for next DMA transfer */ temp = adc->nextIn + 2*adc->fragSize; if (temp >= adc->fragTotalSize) { - MIPS_ASSERT( (temp == adc->fragTotalSize) || + ASSERT( (temp == adc->fragTotalSize) || (temp == adc->fragTotalSize + adc->fragSize) ); temp -= adc->fragTotalSize; } @@ -687,7 +695,7 @@ /* adjust nextIn */ adc->nextIn += adc->fragSize; if (adc->nextIn >= adc->fragTotalSize) { - MIPS_ASSERT(adc->nextIn == adc->fragTotalSize); + ASSERT(adc->nextIn == adc->fragTotalSize); adc->nextIn = 0; } @@ -706,13 +714,13 @@ unsigned temp; /* next DMA transfer should already started */ - MIPS_ASSERT(inl(s->io + VRC5477_DAC1_CTRL) & VRC5477_DMA_WIP); - MIPS_ASSERT(inl(s->io + VRC5477_DAC2_CTRL) & VRC5477_DMA_WIP); + ASSERT(inl(s->io + VRC5477_DAC1_CTRL) & VRC5477_DMA_WIP); + ASSERT(inl(s->io + VRC5477_DAC2_CTRL) & VRC5477_DMA_WIP); /* let us set for next next DMA transfer */ temp = dac->nextOut + dac->fragSize*2; if (temp >= dac->fragTotalSize) { - MIPS_ASSERT( (temp == dac->fragTotalSize) || + ASSERT( (temp == dac->fragTotalSize) || (temp == dac->fragTotalSize + dac->fragSize) ); temp -= dac->fragTotalSize; } @@ -728,22 +736,22 @@ printk("assert fail: - %d vs %d\n", *(u16*)(dac->lbuf + dac->nextOut), outTicket); - MIPS_ASSERT(1 == 0); + ASSERT(1 == 0); } #endif /* adjust nextOut pointer */ dac->nextOut += dac->fragSize; if (dac->nextOut >= dac->fragTotalSize) { - MIPS_ASSERT(dac->nextOut == dac->fragTotalSize); + ASSERT(dac->nextOut == dac->fragTotalSize); dac->nextOut = 0; } /* adjust count */ dac->count -= dac->fragSize; if (dac->count <=0 ) { - MIPS_ASSERT(dac->count == 0); - MIPS_ASSERT(dac->nextIn == dac->nextOut); + ASSERT(dac->count == 0); + ASSERT(dac->nextIn == dac->nextOut); /* buffer under run */ stop_dac(s); } @@ -751,12 +759,12 @@ #if defined(VRC5477_AC97_VERBOSE_DEBUG) if (dac->count) { outTicket ++; - MIPS_ASSERT(*(u16*)(dac->lbuf + dac->nextOut) == outTicket); + ASSERT(*(u16*)(dac->lbuf + dac->nextOut) == outTicket); } #endif /* we cannot have both under run and someone is waiting on us */ - MIPS_ASSERT(! (waitqueue_active(&dac->wait) && (dac->count <= 0)) ); + ASSERT(! (waitqueue_active(&dac->wait) && (dac->count <= 0)) ); /* wake up anybody listening */ if (waitqueue_active(&dac->wait)) @@ -911,7 +919,7 @@ copyCount -= count; bufStart += count; - MIPS_ASSERT(bufStart <= db->fragTotalSize); + ASSERT(bufStart <= db->fragTotalSize); buffer += count *2; } return 0; @@ -943,12 +951,12 @@ } if (copyCount + db->nextOut > db->fragTotalSize) { copyCount = db->fragTotalSize - db->nextOut; - MIPS_ASSERT((copyCount % db->fragSize) == 0); + ASSERT((copyCount % db->fragSize) == 0); } copyFragCount = (copyCount-1) >> db->fragShift; copyFragCount = (copyFragCount+1) << db->fragShift; - MIPS_ASSERT(copyFragCount >= copyCount); + ASSERT(copyFragCount >= copyCount); /* we copy differently based on adc channels */ if (s->adcChannels == 1) { @@ -971,12 +979,12 @@ db->nextOut += copyFragCount; if (db->nextOut >= db->fragTotalSize) { - MIPS_ASSERT(db->nextOut == db->fragTotalSize); + ASSERT(db->nextOut == db->fragTotalSize); db->nextOut = 0; } - MIPS_ASSERT((copyFragCount % db->fragSize) == 0); - MIPS_ASSERT( (count == 0) || (copyCount == copyFragCount)); + ASSERT((copyFragCount % db->fragSize) == 0); + ASSERT( (count == 0) || (copyCount == copyFragCount)); } spin_lock_irqsave(&s->lock, flags); @@ -1005,7 +1013,7 @@ if (!access_ok(VERIFY_WRITE, buffer, count)) return -EFAULT; - MIPS_ASSERT(db->ready); + ASSERT(db->ready); while (count > 0) { // wait for samples in capture buffer @@ -1030,7 +1038,7 @@ } } while (avail <= 0); - MIPS_ASSERT( (avail % db->fragSize) == 0); + ASSERT( (avail % db->fragSize) == 0); copyCount = copy_adc_to_user(s, buffer, count, avail); if (copyCount <=0 ) { if (!ret) ret = -EFAULT; @@ -1053,7 +1061,7 @@ struct dmabuf *db = &s->dma_dac; int bufStart = db->nextIn; - MIPS_ASSERT(db->ready); + ASSERT(db->ready); for (; copyCount > 0; ) { int i; @@ -1071,7 +1079,7 @@ copyCount -= count; bufStart += count; - MIPS_ASSERT(bufStart <= db->fragTotalSize); + ASSERT(bufStart <= db->fragTotalSize); buffer += count *2; } return 0; @@ -1107,13 +1115,13 @@ } if (copyCount + db->nextIn > db->fragTotalSize) { copyCount = db->fragTotalSize - db->nextIn; - MIPS_ASSERT((copyCount % db->fragSize) == 0); - MIPS_ASSERT(copyCount > 0); + ASSERT((copyCount % db->fragSize) == 0); + ASSERT(copyCount > 0); } copyFragCount = (copyCount-1) >> db->fragShift; copyFragCount = (copyFragCount+1) << db->fragShift; - MIPS_ASSERT(copyFragCount >= copyCount); + ASSERT(copyFragCount >= copyCount); /* we copy differently based on the number channels */ if (s->dacChannels == 1) { @@ -1153,12 +1161,12 @@ db->nextIn += copyFragCount; if (db->nextIn >= db->fragTotalSize) { - MIPS_ASSERT(db->nextIn == db->fragTotalSize); + ASSERT(db->nextIn == db->fragTotalSize); db->nextIn = 0; } - MIPS_ASSERT((copyFragCount % db->fragSize) == 0); - MIPS_ASSERT( (count == 0) || (copyCount == copyFragCount)); + ASSERT((copyFragCount % db->fragSize) == 0); + ASSERT( (count == 0) || (copyCount == copyFragCount)); } spin_lock_irqsave(&s->lock, flags); @@ -1168,7 +1176,7 @@ } /* nextIn should not be equal to nextOut unless we are full */ - MIPS_ASSERT( ( (db->count == db->fragTotalSize) && + ASSERT( ( (db->count == db->fragTotalSize) && (db->nextIn == db->nextOut) ) || ( (db->count < db->fragTotalSize) && (db->nextIn != db->nextOut) ) ); @@ -1216,7 +1224,7 @@ } } while (avail <= 0); - MIPS_ASSERT( (avail % db->fragSize) == 0); + ASSERT( (avail % db->fragSize) == 0); copyCount = copy_dac_from_user(s, buffer, count, avail); if (copyCount < 0) { if (!ret) ret = -EFAULT; @@ -1257,7 +1265,7 @@ return mask; } -#ifdef CONFIG_LL_DEBUG +#ifdef VRC5477_AC97_DEBUG static struct ioctl_str_t { unsigned int cmd; const char* str; @@ -1308,7 +1316,7 @@ int count; int val, ret; -#ifdef CONFIG_LL_DEBUG +#ifdef VRC5477_AC97_DEBUG for (count=0; count> 16) & 0x7f) ); + ASSERT(addr == ((result >> 16) & 0x7f) ); return result & 0xffff; } @@ -1828,7 +1836,7 @@ while (myinl(VRC5477_CODEC_WR) & 0x80000000); for (i=0; i< 0x40; i+=4) { - MIPS_ASSERT(inl(s->io+i) == myinl(i)); + ASSERT(inl(s->io+i) == myinl(i)); } printk("codec registers : "); @@ -1856,8 +1864,6 @@ struct vrc5477_ac97_state *s; char proc_str[80]; - MIPS_DEBUG(printk("vrc5477_ac97_probe() invoked\n")); - if (pcidev->irq == 0) return -1; @@ -1909,37 +1915,27 @@ register_sound_mixer(&vrc5477_ac97_mixer_fops, -1)) < 0) goto err_dev2; -#ifdef CONFIG_LL_DEBUG +#ifdef VRC5477_AC97_DEBUG /* intialize the debug proc device */ s->ps = create_proc_read_entry(VRC5477_AC97_MODULE_NAME, 0, NULL, proc_vrc5477_ac97_dump, NULL); -#endif /* CONFIG_LL_DEBUG */ +#endif /* VRC5477_AC97_DEBUG */ /* enable pci io and bus mastering */ if (pci_enable_device(pcidev)) goto err_dev3; pci_set_master(pcidev); -/* -jsun_scan_pci_bus(); -vrc5477_show_pci_regs(); -vrc5477_show_pdar_regs(); -*/ - /* cold reset the AC97 */ outl(VRC5477_ACLINK_CTRL_RST_ON | VRC5477_ACLINK_CTRL_RST_TIME, s->io + VRC5477_ACLINK_CTRL); while (inl(s->io + VRC5477_ACLINK_CTRL) & VRC5477_ACLINK_CTRL_RST_ON); -/* -jsun_ac97_test(s); -*/ - /* codec init */ if (!ac97_probe_codec(&s->codec)) goto err_dev3; -#ifdef CONFIG_LL_DEBUG +#ifdef VRC5477_AC97_DEBUG sprintf(proc_str, "driver/%s/%d/ac97", VRC5477_AC97_MODULE_NAME, s->codec.id); s->ac97_ps = create_proc_read_entry (proc_str, 0, NULL, @@ -1994,10 +1990,12 @@ if (!s) return; list_del(&s->devs); -#ifdef CONFIG_LL_DEBUG + +#ifdef VRC5477_AC97_DEBUG if (s->ps) remove_proc_entry(VRC5477_AC97_MODULE_NAME, NULL); -#endif /* CONFIG_LL_DEBUG */ +#endif /* VRC5477_AC97_DEBUG */ + synchronize_irq(); free_irq(s->irq, s); release_region(s->io, pci_resource_len(dev,0)); diff -Nru linux/include/asm-mips/ddb5xxx/debug.h.orig linux/include/asm-mips/ddb5xxx/debug.h --- linux/include/asm-mips/ddb5xxx/debug.h.orig Mon Oct 8 11:09:08 2001 +++ linux/include/asm-mips/ddb5xxx/debug.h Mon Oct 8 17:34:32 2001 @@ -1,42 +0,0 @@ -/*********************************************************************** - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * include/asm-mips/ddb5xxx/debug.h - * Some debug macros used by ddb code. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - *********************************************************************** - */ - -#ifndef __ASM_DDB5XXX_DEBUG_H -#define __ASM_DDB5XXX_DEBUG_H - -#include - -/* - * macro for catching spurious errors. Eable to LL_DEBUG in kernel hacking - * config menu. - */ -#ifdef CONFIG_LL_DEBUG - -#include - -#define MIPS_ASSERT(x) if (!(x)) { panic("MIPS_ASSERT failed at %s:%d\n", __FILE__, __LINE__); } -#define MIPS_VERIFY(x, y) MIPS_ASSERT(x y) -#define MIPS_DEBUG(x) do { x; } while (0) - -#else - -#define MIPS_ASSERT(x) -#define MIPS_VERIFY(x, y) x -#define MIPS_DEBUG(x) - -#endif - -#endif /* __ASM_DDB5XXX_DEBUG_H */ diff -Nru linux/include/asm-mips/ddb5xxx/ddb5xxx.h.orig linux/include/asm-mips/ddb5xxx/ddb5xxx.h --- linux/include/asm-mips/ddb5xxx/ddb5xxx.h.orig Mon Oct 8 18:17:04 2001 +++ linux/include/asm-mips/ddb5xxx/ddb5xxx.h Mon Oct 8 18:42:35 2001 @@ -21,8 +21,6 @@ #include #include -#include - /* * This file is based on the following documentation: * diff -Nru linux/include/asm-mips/debug.h.orig linux/include/asm-mips/debug.h --- linux/include/asm-mips/debug.h.orig Mon Oct 8 17:34:43 2001 +++ linux/include/asm-mips/debug.h Tue Oct 9 09:58:41 2001 @@ -0,0 +1,48 @@ +/* + * Debug macros for run-time debugging. Turned on/off with CONFIG_DEBUG option. + * + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef _ASM_DEBUG_H +#define _ASM_DEBUG_H + +#include + +/* + * run-time macros for catching spurious errors. Eable CONFIG_DEBUG in + * kernel hacking config menu to use them. + * + * Use them as run-time debugging aid. NEVER USE THEM AS ERROR HANDLING CODE!!! + */ + +#ifdef CONFIG_DEBUG + +#include + +#define db_assert(x) if (!(x)) { \ + panic("assertion failed at %s:%d: %s\n", __FILE__, __LINE__, #x); } +#define db_warn(x) if (!(x)) { \ + printk(KERN_WARNING "warning at %s:%d: %s\n", __FILE__, __LINE__, #x); } +#define db_verify(x, y) db_assert(x y) +#define db_verify_warn(x, y) db_warn(x y) +#define db_run(x) do { x; } while (0) + +#else + +#define db_assert(x) +#define db_warn(x) +#define db_verify(x, y) x +#define db_verify_warn(x, y) x +#define db_run(x) + +#endif + +#endif /* _ASM_DEBUG_H */