diff -Nru linux/arch/mips/kernel/setup.c.orig linux/arch/mips/kernel/setup.c --- linux/arch/mips/kernel/setup.c.orig Thu Jul 12 16:58:47 2001 +++ linux/arch/mips/kernel/setup.c Mon Jul 30 11:30:32 2001 @@ -191,6 +191,12 @@ MIPS_CPU_WATCH | MIPS_CPU_VCE; mips_cpu.tlbsize = 48; break; + case PRID_IMP_VR41XX: + mips_cpu.cputype = CPU_VR41XX; + mips_cpu.isa_level = MIPS_CPU_ISA_III; + mips_cpu.options = R4K_OPTS; + mips_cpu.tlbsize = 32; + break; case PRID_IMP_R4600: mips_cpu.cputype = CPU_R4600; mips_cpu.isa_level = MIPS_CPU_ISA_III; diff -Nru linux/arch/mips/kernel/head.S.orig linux/arch/mips/kernel/head.S --- linux/arch/mips/kernel/head.S.orig Thu Jul 5 14:20:33 2001 +++ linux/arch/mips/kernel/head.S Mon Jul 30 14:24:31 2001 @@ -76,7 +76,11 @@ addu k1, k1, k0 # add in pgd offset mfc0 k0, CP0_CONTEXT # get context reg lw k1, (k1) +#if defined(CONFIG_CPU_VR41XX) + srl k0, k0, 3 # get pte offset +#else srl k0, k0, 1 # get pte offset +#endif and k0, k0, 0xff8 addu k1, k1, k0 # add in offset lw k0, 0(k1) # get even pte diff -Nru linux/arch/mips/mm/r4xx0.c.orig linux/arch/mips/mm/r4xx0.c --- linux/arch/mips/mm/r4xx0.c.orig Tue Jul 24 13:35:39 2001 +++ linux/arch/mips/mm/r4xx0.c Mon Jul 30 11:28:00 2001 @@ -2111,10 +2111,6 @@ #undef DEBUG_TLB #undef DEBUG_TLBUPDATE -#define NTLB_ENTRIES 48 /* Fixed on all R4XX0 variants... */ - -#define NTLB_ENTRIES_HALF 24 /* Fixed on all R4XX0 variants... */ - void flush_tlb_all(void) { unsigned long flags; @@ -2136,7 +2132,7 @@ entry = get_wired(); /* Blast 'em all away. */ - while(entry < NTLB_ENTRIES) { + while(entry < mips_cpu.tlbsize) { set_index(entry); BARRIER; tlb_write_indexed(); @@ -2178,7 +2174,7 @@ __save_and_cli(flags); size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; size = (size + 1) >> 1; - if(size <= NTLB_ENTRIES_HALF) { + if(size <= mips_cpu.tlbsize/2) { int oldpid = (get_entryhi() & 0xff); int newpid = (mm->context & 0xff); @@ -2406,7 +2402,14 @@ /* Detect and size the various r4k caches. */ static void __init probe_icache(unsigned long config) { - icache_size = 1 << (12 + ((config >> 9) & 7)); + switch (mips_cpu.cputype) { + case CPU_VR41XX: + icache_size = 1 << (10 + ((config >> 9) & 7)); + break; + default: + icache_size = 1 << (12 + ((config >> 9) & 7)); + break; + } ic_lsize = 16 << ((config >> 5) & 1); printk("Primary instruction cache %dkb, linesize %d bytes.\n", @@ -2415,7 +2418,14 @@ static void __init probe_dcache(unsigned long config) { - dcache_size = 1 << (12 + ((config >> 6) & 7)); + switch (mips_cpu.cputype) { + case CPU_VR41XX: + dcache_size = 1 << (10 + ((config >> 6) & 7)); + break; + default: + dcache_size = 1 << (12 + ((config >> 6) & 7)); + break; + } dc_lsize = 16 << ((config >> 4) & 1); printk("Primary data cache %dkb, linesize %d bytes.\n", diff -Nru linux/arch/mips/config.in.orig linux/arch/mips/config.in --- linux/arch/mips/config.in.orig Tue Jul 24 13:35:35 2001 +++ linux/arch/mips/config.in Mon Jul 30 11:38:31 2001 @@ -20,6 +20,7 @@ bool 'Support for BAGET MIPS series (EXPERIMENTAL)' CONFIG_BAGET_MIPS bool 'Support for DECstations (EXPERIMENTAL)' CONFIG_DECSTATION bool 'Support for NEC DDB Vrc-5074 (EXPERIMENTAL)' CONFIG_DDB5074 + bool 'Support for NEC Osprey board (EXPERIMENTAL)' CONFIG_NEC_OSPREY bool 'Support for Galileo EV96100 Evaluation board' CONFIG_MIPS_EV96100 bool 'Support for Galileo EV64120 Evaluation board' CONFIG_MIPS_EV64120 if [ "$CONFIG_MIPS_EV64120" = "y" ]; then @@ -184,6 +185,14 @@ define_bool CONFIG_NEW_TIME_C y define_bool CONFIG_NEW_IRQ y fi +if [ "$CONFIG_NEC_OSPREY" = "y" ]; then + define_bool CONFIG_CPU_VR41XX y + define_bool CONFIG_CPU_R4X00 y + define_bool CONFIG_VR4181 y + define_bool CONFIG_ISA y + define_bool CONFIG_SERIAL y + define_bool CONFIG_SCSI n +fi if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then define_bool CONFIG_PCI y define_bool CONFIG_IT8712 y @@ -249,7 +258,8 @@ bool ' lld/scd Instructions available' CONFIG_CPU_HAS_LLDSCD bool ' Writeback Buffer available' CONFIG_CPU_HAS_WB else - if [ "$CONFIG_CPU_R3000" = "y" ]; then + if [ "$CONFIG_CPU_R3000" = "y" -o + "$CONFIG_CPU_VR41XX" = "y" ]; then if [ "$CONFIG_DECSTATION" = "y" ]; then define_bool CONFIG_CPU_HAS_LLSC n define_bool CONFIG_CPU_HAS_LLDSCD n @@ -278,7 +288,8 @@ if [ "$CONFIG_DECSTATION" = "y" -o \ "$CONFIG_DDB5074" = "y" -o \ "$CONFIG_DDB5476" = "y" -o \ - "$CONFIG_NINO" = "y" ]; then + "$CONFIG_NINO" = "y" -o \ + "$CONFIG_NEC_OSPREY" = "y" ]; then define_bool CONFIG_CPU_LITTLE_ENDIAN y else bool 'Generate little endian code' CONFIG_CPU_LITTLE_ENDIAN diff -Nru linux/include/asm-mips/cpu.h.orig linux/include/asm-mips/cpu.h --- linux/include/asm-mips/cpu.h.orig Thu Jul 12 17:02:57 2001 +++ linux/include/asm-mips/cpu.h Mon Jul 30 11:46:53 2001 @@ -45,6 +45,7 @@ #define PRID_IMP_R6000A 0x0600 #define PRID_IMP_R10000 0x0900 #define PRID_IMP_R4300 0x0b00 +#define PRID_IMP_VR41XX 0x0c00 #define PRID_IMP_R12000 0x0e00 #define PRID_IMP_R8000 0x1000 #define PRID_IMP_R4600 0x2000 @@ -53,11 +54,11 @@ #define PRID_IMP_R4640 0x2200 #define PRID_IMP_R4650 0x2200 /* Same as R4640 */ #define PRID_IMP_R5000 0x2300 -#define PRID_IMP_R5432 0x5400 #define PRID_IMP_SONIC 0x2400 #define PRID_IMP_MAGIC 0x2500 #define PRID_IMP_RM7000 0x2700 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ +#define PRID_IMP_R5432 0x5400 #define PRID_IMP_4KC 0x8000 #define PRID_IMP_5KC 0x8100 #define PRID_IMP_4KEC 0x8400 diff -Nru linux/include/asm-mips/bootinfo.h.orig linux/include/asm-mips/bootinfo.h --- linux/include/asm-mips/bootinfo.h.orig Tue Jul 24 13:36:13 2001 +++ linux/include/asm-mips/bootinfo.h Mon Jul 30 11:40:30 2001 @@ -31,10 +31,12 @@ #define MACH_GROUP_SIBYTE 16 /* Sibyte Eval Boards */ #define MACH_GROUP_TOSHIBA 17 /* Toshiba Reference Systems TSBREF */ #define MACH_GROUP_ALCHEMY 18 /* Alchemy Semi Eval Boards*/ +#define MACH_GROUP_NEC_VR41XX 19 /* NEC Vr41xx based boards/gadgets */ #define GROUP_NAMES { "unknown", "Jazz", "Digital", "ARC", "SNI", "ACN", \ "SGI", "Cobalt", "NEC DDB", "Baget", "Cosine", "Galileo", "Momentum", \ - "ITE", "Philips", "Globepspan", "SiByte", "Toshiba", "Alchemy" } + "ITE", "Philips", "Globepspan", "SiByte", "Toshiba", "Alchemy", \ + "NEC Vr41xx" } /* * Valid machtype values for group unknown (low order halfword of mips_machtype) @@ -195,6 +197,14 @@ #define GROUP_ALCHEMY_NAMES { "PB1000" } /* the actual board name */ /* + * Valid machtype for group NEC_VR41XX + */ +#define MACH_NEC_OSPREY 0 /* Osprey eval board */ +#define MACH_NEC_EAGLE 1 /* NEC Eagle board */ + +#define GROUP_NEC_VR41XX_NAMES { "Osprey", "Eagle" } + +/* * Valid cputype values */ #define CPU_UNKNOWN 0 @@ -237,7 +247,9 @@ #define CPU_AU1000 37 #define CPU_4KEC 38 #define CPU_4KSC 39 -#define CPU_LAST 39 +#define CPU_VR41XX 40 +#define CPU_LAST 40 + #define CPU_NAMES { "unknown", "R2000", "R3000", "R3000A", "R3041", "R3051", \ "R3052", "R3081", "R3081E", "R4000PC", "R4000SC", "R4000MC", \ @@ -245,7 +257,7 @@ "R6000A", "R8000", "R10000", "R4300", "R4650", "R4700", "R5000", \ "R5000A", "R4640", "Nevada", "RM7000", "R5432", "MIPS 4Kc", \ "MIPS 5Kc", "R4310", "SiByte SB1", "TX3912", "TX3922", "TX3927", \ - "Au1000", "MIPS 4KEc", "MIPS 4KSc" } + "Au1000", "MIPS 4KEc", "MIPS 4KSc", "NEC Vr41xx" } #define COMMAND_LINE_SIZE 256 diff -Nru linux/include/asm-mips/mipsregs.h.orig linux/include/asm-mips/mipsregs.h --- linux/include/asm-mips/mipsregs.h.orig Tue Jul 24 13:36:14 2001 +++ linux/include/asm-mips/mipsregs.h Mon Jul 30 11:46:53 2001 @@ -139,6 +139,14 @@ /* * Values for PageMask register */ +#include +#ifdef CONFIG_CPU_VR41XX +#define PM_1K 0x00000000 +#define PM_4K 0x00001800 +#define PM_16K 0x00007800 +#define PM_64K 0x0001f800 +#define PM_256K 0x0007f800 +#else #define PM_4K 0x00000000 #define PM_16K 0x00006000 #define PM_64K 0x0001e000 @@ -146,6 +154,7 @@ #define PM_1M 0x001fe000 #define PM_4M 0x007fe000 #define PM_16M 0x01ffe000 +#endif /* * Values used for computation of new tlb entries diff -Nru linux/include/asm-mips/pgtable.h.orig linux/include/asm-mips/pgtable.h --- linux/include/asm-mips/pgtable.h.orig Fri Jul 20 11:03:30 2001 +++ linux/include/asm-mips/pgtable.h Mon Jul 30 11:46:53 2001 @@ -334,7 +334,11 @@ * is simple. */ #define page_address(page) ((page)->virtual) +#ifdef CONFIG_CPU_VR41XX +#define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> (PAGE_SHIFT + 2)))) +#else #define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> PAGE_SHIFT))) +#endif /* * The following only work if pte_present() is true. @@ -405,6 +409,17 @@ * Conversion functions: convert a page and protection to a page entry, * and a page entry and page directory to the page they refer to. */ +#ifdef CONFIG_CPU_VR41XX +#define mk_pte(page, pgprot) \ +({ \ + pte_t __pte; \ + \ + pte_val(__pte) = ((unsigned long)(page - mem_map) << (PAGE_SHIFT + 2)) | \ + pgprot_val(pgprot); \ + \ + __pte; \ +}) +#else #define mk_pte(page, pgprot) \ ({ \ pte_t __pte; \ @@ -414,10 +429,15 @@ \ __pte; \ }) +#endif extern inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) { +#ifdef CONFIG_CPU_VR41XX + return __pte((physpage << 2) | pgprot_val(pgprot)); +#else return __pte(physpage | pgprot_val(pgprot)); +#endif } extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)